The present invention relates to a method for manufacturing a semiconductor device and, more particularly to, a silicon-based heterodyne-junction bipolar transistor made of silicon or germanium mainly.
The performance of an operating speed of the bipolar transistors depends on a variety of kinds of parasitic resistance and parasitic capacitance and also a carrier transit time in an intrinsic base region. These items can be classified into a few factors, of which the base resistance (Rb), the collector-base junction capacitance (Ctc), and the carrier transit time in the intrinsic base region (xcfx84F) may be said to be highly contributive parameters. The parameter xcfx84F is closely related to a maximum cut-off frequency (fTmax), which is a measurement value. The device construction of the transistors may be said to have been developed along a guideline for improving these parameters.
The specific method to improve the parameter fTmax is to reduce a base width, so that in a typical vertical device construction an important technology has been how to form a shallow junction base in the developments of high-speed bipolar transistors. A base junction with a depth of 0.1 xcexcm or less has been realized by an ion injection method of injecting ions of boron or boron di-fluoride (BF2) at injection energy of 10 KeV, a solid phase diffusion method of diffusion from a solid phase of boron glass, etc. and so is mass-produced presently with an fTmax value of 30-50 GHz or so.
A trial to further reduce the thickness of the base layer by promoting these technologies leads to a problem of deteriorated punch-through breakdown voltage. The punch-through breakdown voltage refers to such a punch-through phenomenon that a reverse-biased voltage applied to the collector causes a collector""s depletion layer to spread and reach an emitter""s depletion layer and so occurs more frequently as the base layer is more reduced in film thickness. To avoid this phenomenon, it is indispensable to increase the concentration of a base carrier. An increase in the base carrier concentration, however, decreases its ratio with respect to an emitter carrier concentration already set at a solid solution level to increase a degree of reverse injection of holes from the base layer to the emitter layer, thus decreasing a current amplification factor, which is a ratio between a base current and a collector current. This provides a physical limit of the performance of the silicon (Si)-based bipolar transistors, so that a practical speed performance limit of this type of devices has generally been considered to be 70-80 GHz as fTmax.
To break through this performance barrier which has been considered to be a limit, such a technology has been suggested by IBM near the end of 1980s. It is an invention of a silicon-germanium hetero-junction bipolar transistor (Si-Ge-HBT). The present invention is based on such a technology that Ge having a smaller band gap (Eg) than silicon is mixed into the base layer by about 10% to thereby narrow the band gap (Eg) of the base layer. Since Si and Ge have a band gap difference therebetween, the composition ratio can be changed from 0% to 100% continuously through thorough solid solution to Si.
A literature says that in the strain state (range in which the lattice is not relaxed), a band gap change with respect to a Ge composition is xe2x88x927.3 meV/Ge% for pure Si. Taking into account that thermal energy of the room temperature is about 27 meV, even such a degree of band gap difference makes up a potential barrier against reverse injection of holes from the base to the emitter, thus providing a factor that can independently control an injection efficiency, which has been determined by a difference in carrier concentration between the emitter and the base. As a result, even in a case where the carrier concentration ratio is reversed between the base and the emitter, it is possible to obtain a current amplification factor (hFE) of 100 or more.
As mentioned above, an HBT with a base band gap reduced by mixture of Ge into Si is capable of avoiding a decrease in the current amplification factor even with an increase in the base concentration to thereby further reduce the film thickness of the base width, thus resulting in a great increase in the fTmax. Furthermore, it can enjoy a decrease in the resistivity of the intrinsic base, thus improving the overall speed performance indicated by fTmax/(RbXCtc).
The following will describe a manufacturing method and a profile structure by use of a typical conventional technology. FIG. 19 shows a profile structure. FIGS. 20 show cross-sectional views of a transistor before and-after the base layer undergoes selective epitaxial growth. In order to improve the performance including external base resistance, a described self-alignment type construction of transistors is necessary. First, in a P type Si substrate 1901 with surface orientation (100) is formed a buried N+ type layer, on a surface of which is grown an N type epitaxial layer. On the Si substrate 1901 are also adhered a thermal oxide film 1902, and a boron-doped poly-crystal silicon layer 1903 sequentially. An opening is formed through the boron-doped P+ type poly-crystal Si layer 1903 and the thermal oxide film 1902, after which a silicon nitride film 1904 is adhered and etched in an anisotropic manner to form a side wall (SW) formed of a nitride film and a silicon nitride film SW1905 as shown in FIG. 20A.
Then, a Si-Ge layer and a Si layer are grown in an selective epitaxial manner. Prior to this selective epitaxial growth, the surface is cleared of a natural oxide film adhered thereto by washing it with diluted hydrofluoric acid (HF) and then thermally treated at 900xc2x0 C. in a hydrogen atmosphere with water and oxygen regulated at 10 ppb or less at 15 Torr for five minutes or so. This thermal treatment is carried out to completely remove the natural oxide film formed after washing with HF. Then, the temperature is lowered to 650xc2x0 C. or so, after which are introduced di-chloro silage (SiH2Cl2) as a Si source gas, germanium hydride (GeH4) as a Ge source gas, phosphorous hydride (PH3) as an N type doping gas, and diborane (B2H6) as a P type doping gas, followed by a hydrogen chloride (HCl) gas to reserve growth selectivity with respect to the silicon nitride film and the silicon oxide film, thus carrying out epitaxial growth.
In a first process step of growing the Si-Ge layer, the Ge concentration is controlled to have a gradient such that it may be 15% on the collector and 5% on the emitter side. This control is conducted by changing a flow rate of GeH4 continuously. The growth rate in this temperature range, however, is determined by the concentration of GeH4 in the atmosphere, so that the control needs to be conducted taking this into account.
As for conductivity types, first an M type Si-Ge layer (1906) into which phosphorus (P) is doped at a value a little less than 1E17 atoms/cm3 is grown to thickness of 40 nm, then a P type Si-Ge layer (1909) into which boron (B) is doped at about 1E19 atoms/cm3 is grown to thickness of 10 nm, and finally a non-doped Si-Ge layer is grown to thickness of 10 nm. As a result, a Si-Ge layer with thickness of about 60 nm is grown. In this step, also from the boron-doped P+ type poly-crystal Si layer (1903), a base link portion diffusion layer (1907) of the P type poly-crystal Si by self-alignment grows to link with the N type Si-Ge layer (1906) grown from the Si substrate (1901).
Next, the temperature is raised to 700xc2x0 C. to then grow a cap Si layer (1908). It is a pure silicon layer having film thickness of 30 nm containing no Ge. A cross-sectional view of this step is shown in FIG. 20B. Thus, a series of epitaxial processes is used to form the active regions of the transistor and establish contact between these regions and the P+ type boron-doped poly-crystal Si layer which provides the base electrode. The subsequent process is used to generate N+ type emitter poly-crystal Si and carry out annealing treatment (RTA: Rapid Thermal Annealing) to diffuse phosphorus (P) into the Si layer, thus forming a hetero-junction.
As described above, by using a Si-Ge as the base layer, it is possible to manufacture a transistor with a base width of 300 xc3x85 with a base peak carrier concentration being 1E19 atoms/cm3 and also to obtain an effect of electric field acceleration of the carrier, thus realizing a fTmax in excess of 100 GHz.
The operating speed of the devices, however, is desired to be higher and higher with a demand for a rapid increase in transmission capacity in, for example, an application of information communication. Taking into account that a compound-based device made of gallium arsenic (GaAs) or indium phosphorus (InP) already has a performance speed of 200 GHz as fmax, even such a silicon-based bipolar transistor as to have a speed of 100 GHz may not be considered to be excellent in speed performance and is demanded to be higher in speed. The silicon-based bipolar transistor, however, is relatively inexpensive in manufacture and stable in quality and so may be said to be highly superior in performance/cost ratio if it has almost the same speed performance as the compound-based device.
Furthermore, owing to the developments of the Si-Ge-HBT, the physical limit of the-device may be said to be dependent on the solid solubility of boron in the base. If the solid solubility of boron in the Si base is supposed to be 1E2 through 1E2 atoms/cm3 or so, a concentration of only {fraction (1/10)} of this value is realized in the present-day Si-Ge-HBT. In this view, if a high peak concentration can be realized by any process, sufficient punch-through breakdown voltage and current amplification factor should be obtained even if the base width is reduced to 150 xc3x85 or less. If a Si-Ge-HBT having such a profile structure is realized, it may be possible to obtain speed performance at least the same as that of the compound-based device.
In view of the above-mentioned problems of the conventional Si-Ge-HBT, the present invention may increase such a concentration of boron in a base layer as not to have reached possible highest solid solubility in Si, and may decrease film thickness of the base layer, thus realizing as much as possible such a physical limit value of speed performance of a Si-Ge-HBT as not to have been established yet. Further, the present invention may provide a novel and improved semiconductor device and method for manufacturing the same for giving high reproducibility of that high performance even in mass-production and stable device characteristics.
In a method for manufacturing a semiconductor device, an N type single-crystal silicon substrate having a first silicon oxide film and a P type poly-crystal silicon layer is provided. A silicon nitride film is formed on the P type poly-crystal silicon layer. A side wall of the silicon nitride film is formed in an opening in the P type poly-crystal silicon layer above a portion expected to provide an active region. The first silicon oxide film-has an opening therein which is larger than the opening formed in the P type poly-crystal silicon layer. Then, an N type IV-group semiconductor mixed crystal layer having a smaller band gap than silicon to a desired thickness is grown on the-single-crystal silicon substrate on which a surface of the portion expected to provide said active region is exposed. A non-doped single-crystal silicon layer is grown on the IV-group semiconductor mixed crystal layer to a desired thickness. Then, boron is diffused at a desired concentration from a surface of the non-doped single-crystal silicon layer. A side wall containing a second silicon oxide film is formed on an inner side of the side wall of the silicon nitride film. Finally, a phosphorus-doped N type poly-crystal silicon layer is grown throughout on the surface to perform processing and phosphorus diffusion on said N type poly-crystal silicon layer in order to provide an emitter electrode.